1. Field of the Invention
The present invention relates generally to a DRAM memory cell and its manufacturing method and, more particularly, to a self-aligned trench-type DRAM structure and its manufacturing methods.
2. Description of Related Art
A dynamic random-access-memory (DRAM) cell including an access transistor and a storage capacitor has become the most important storage element in electronic system, especially in computer and communication system. The DRAM density is increased very rapidly in order to decrease the cost per bit and, therefore, an advanced photolithography is needed to decrease the minimum-feature-size (F) of a cell.
The output voltage of a DRAM cell is proportional to the capacitance value of the storage capacitor of the DRAM cell and, therefore, the storage capacitor must have a satisfactory capacitance value to have stable operation of the cell as the applied voltage is scaled. Basically, the storage capacitor can be implemented in a trench-type or a stack-type. The trench-type is formed by forming a deep trench in a semiconductor substrate without increasing the surface area of the semiconductor-substrate surface; however, the deep-trench formation becomes very difficult as the minimum-feature-size is smaller than 0.15 xcexcm. The stack-type is formed by implementing a capacitor structure over the access transistor and its nearby dummy-transistor structure through the conductive contact-plug over the node diffusion region of the access transistor; however, the finite surface area over the access transistor becomes very difficult for forming a complicate capacitor structure as the minimum-feature-size is smaller than 0.15 xcexcm.
Basically, the cell size of the stack-type DRAM is limited by a dummy transistor being formed over the isolation region. Accordingly, the limit cell size of the stack-type DRAM is 8F2 for shallow-trench-isolation. However, the cell size of a trench-type DRAM is limited by the space between nearby deep-trench capacitors and the separation between the access transistor and the deep-trench capacitor. Therefore, the limit cell size of a trench-type DRAM is also 8F2 if the separation between the access transistor and the trench capacitor can""t be minimized.
A typical example of a trench-type DRAM cell is shown in FIG. 1, in which a deep trench is formed in a semiconductor substrate 100. A trench capacitor is formed in the lower portion of the deep trench, in which a lower capacitor node 101 is formed by a heavily-doped n+ diffusion region using arsenic-silicate-glass (ASG) as a diffusion source; an upper capacitor node 103a is made of doped polycrystalline-silicon; and a capacitor-dielectric layer 102 is formed by a composite dielectric layer such as an oxide-nitride-oxide structure or a nitride-oxide structure. An oxide collar 104 is used to separate the lower capacitor node 101 from a source diffusion region 105a, 105b, and a capacitor-node connector 103b being made of doped polycrystalline-silicon is used to electrically connect the upper capacitor node 103a to a source node 103c. The source node 103c is made of heavily-doped polycrystalline-silicon to act as a diffusion source for forming a n+ source diffusion region 105a. A shallow-trench-isolation (STI) region 106 is filled with a CVD-oxide layer in order to separate nearby trench capacitors. Two gate-stacks 108, 109 are formed over an upper surface, in which one gate-stack 108 is acted as a passing word line and another gate-stack 109 being acted as an excess transistor. A common-source diffusion region 105b and a common-drain diffusion region 107 for a bit-line node are formed in an upper surface of the semiconductor substrate 100. From FIG. 1, it is clearly seen that the limit cell size is 8F2 if the space between two nearby trench capacitors is defined to be a minimum-feature-size (F) of technology used. Apparently, the cell size can be further reduced if the separation between two adjacent deep trenches and the common-source region can be reduced. It is, therefore, a major objective of the present invention to offer a self-aligned trench-type DRAM structure for obtaining a cell size of 6F2 or smaller.
It is another objective of the present invention to offer a manufacturing method for forming the self-aligned trench-type DRAM structure with less masking photoresist steps.
It is a further objective of the present invention to offer two different contactless DRAM array structures for high-speed read and write operations.
A self-aligned trench-type DRAM structure and its contactless DRAM arrays are disclosed by the present invention. The self-aligned trench-type DRAM structure comprises a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure, in which the self-aligned DRAM capacitor structure includes a deep-trench capacitor region and a shallow-trench-isolation region being defined by a first sidewall dielectric spacer and the self-aligned DRAM transistor structure includes a scalable gate-stack region and a common-drain region being defined by a third sidewall dielectric spacer. The deep-trench capacitor region comprises a lower capacitor node made of an n+ diffusion region being formed in the lower portion of a deep trench, a capacitor-dielectric layer being formed over the lower capacitor node, an upper capacitor node made of a planarized heavily-doped polycrystalline-silicon layer being formed over the capacitor-dielectric layer, a collar-oxide layer being formed over the capacitor-dielectric layer and a portion of the upper capacitor node, a source conductive layer integrated with a capacitor-node connector being formed on a portion of the upper capacitor node, and a common-source diffusion region being formed by out diffusion of the source conductive layer. The shallow-trench-isolation region being formed outside of the first sidewall dielectric spacer comprises a second-type planarized field-oxide layer with a bottom surface level slightly lower than that of the collar-oxide layer and an n+ diffusion region being formed under the second-type planarized field-oxide layer. A first planarized thick-oxide layer is formed over the deep-trench capacitor region and the second-type planarized field-oxide layer. The scalable gate-stack region comprises from top to bottom a third sidewall dielectric spacer, an elongated conductive-gate layer being acted as a word line, a conductive-gate layer, a gate-dielectric layer, and the common-source diffusion region being formed near the deep-trench capacitor region for forming a first-type DRAM cell; and comprises from top to bottom a planarized conductive-gate island being integrated with a metal word-line, a conductive-gate layer, a gate-dielectric layer, and a common-source diffusion region being formed near the deep-trench capacitor for forming a second-type DRAM cell. The common-drain region comprises a common-drain diffusion region having a shallow heavily-doped diffusion region formed within a lightly-doped diffusion region and a planarized common-drain conductive island integrated with a metal bit-line being formed on the common-drain diffusion region outside of a fourth sidewall dielectric spacer over a sidewall of the scalable gate-stack region for forming the first-type DRAM cell; and comprises a common-drain diffusion region having a shallow heavily-doped diffusion region formed within a lightly-doped diffusion region and a common-drain conductive bit-line being at least formed over the common-drain diffusion region outside of a fourth sidewall dielectric spacer over a sidewall of the scalable gate-stack region for forming the second-type DRAM cell. The cell size of the self-aligned trench-type DRAM structure can be fabricated to be smaller than 6F2.
The self-aligned trench-type DRAM structure of the present invention is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of first-type DRAM cells, a plurality of metal bit-lines integrated with the planarized common-drain conductive islands being patterned to be aligned above a plurality of active regions, and a plurality of elongated conductive-gate layers acted as a plurality of word lines being formed transversely to the plurality of metal bit-lines. A second-type contactless DRAM array comprises a plurality of second-type DRAM cells, a plurality of metal word-lines integrated with the planarized conductive-gate islands being patterned to be aligned above a plurality of active regions, and a plurality of highly conductive common-drain bus lines acted as a plurality of bit-lines being formed transversely to the plurality of metal word-lines.